TIMING ANALYSIS FOR COMBINATIONAL CIRCUITS - Timing - page 96

5

TIMING ANALYSIS FOR
COMBINATIONAL CIRCUITS

5.1 INTRODUCTION

The methods described in Chapter 4 can be employed to find the delay of a
single stage of combinational logic. A larger combinational circuit consists of
several such stages, and the next logical step is to extend these methods for
circuit-level delay calculation. This chapter will present methods that compute
the delay of a combinational logic block in a computationally efficient manner.

5.2 REPRESENTATION OF COMBINATIONAL AND SEQUENTIAL
CIRCUITS
A combinational logic circuit may be represented as a timing graph G = ( V, E ) ,
where the elements of V, the vertex set, are the logic gates in the circuit and
the primary inputs and outputs of the circuit. Strictly speaking, this discussion
should work with channel-connected components instead, but we will press
on with the term “gate,” with the understanding that it is considered to be
equivalent to a component in this context.
A pair of vertices, and are connected by a directed edge
if there is a connection from the output of the element represented by vertex
to the input of the element represented by vertex A simple logic circuit and
its corresponding graph are illustrated in Figure 5.1(a) and (b), respectively.
A simple transform that converts the graph into one that has a single source
and a single sink is often useful. In the event that all primary inputs are