Global Positioning System Reference
In-Depth Information
1
1
0.5
0.5
0
0
−0.5
−0.5
−1
−1.5
−1
−0.5
0
0.5
1
1.5
−1.5
−1
−0.5
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1
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Time Delay [chip]
Time Delay [chip]
FIGURE 2.7. The two triangles indicate the early and the late ACF. In the left part the two
triangles are separated by d
1 chip (classical wide correlator), and the right part shows
a separation of d = 0 . 5 chip (narrow correlator). Both discriminators have the same slope
close to the origin.
=
The Doppler frequency shift on the C/A code is small because of the low
chip rate of the C/A code. The C/A code has a chip rate of 1
.
023 Mhz, which
is 1575
1540 times lower than the L1 carrier frequency. It follows
that the Doppler frequency on the C/A code is 3.2 Hz and 6.4 Hz for the stationary
and the high-speed GPS receiver , respectively.
The Doppler frequency on the C/A code can cause misalignment between the
received and the locally generated codes and the values of the Doppler frequency
are important for the tracking method. We return to this topic in Chapters 6 and 7.
.
42
/
1
.
023
=
2.5
Code Tracking
GPS signal receiving involves a classical problem, namely that one of code track-
ing which can be solved by means of the delay-locked loop (DLL) scheme based
on an early-late discriminator. For more detail on this topic we refer to Chapter 7.
This loop-error detector or loop discriminator is—in its simplest version—based
on a two-correlator structure. Each correlator is set with a small time offset rela-
tive to the promptly received signal code timing phase , both producing early and
late signals. Combining the early and late signals provides an error signal, driving
the loop toward elimination of the delay-tracking error.
The code tracking loop can be designed as a
- coherent delay lock loop (DLL), or a
- noncoherent DLL.
The coherent DLL requires the phase lock loop to be in lock, i.e., it is tracking the
carrier phase and the navigation data bits have been removed from the signal. The
noncoherent DLL is able to track the code with the navigation data bit present and
the PLL is not necessarily in lock. The noncoherent design is the preferred one;
see Winkel (2000).
 
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