Translating JVM Code to MIPS Code - Introduction to Compiler Construction in a Java World - page 227

A full discussion of compiler optimization is outside the scope of this text; see the Further
Readings section (Section 6.4) at the end of this chapter for detailed discussions of code
optimization techniques.
Summary
At a panel discussion on compiler optimization, Kathleen Knobe observed that, rather than
to put all of one's eorts into just one or two optimizations, it is best to attempt all of
them, even if they cannot be done perfectly.
We have not implemented any of these optimizations, but leave them as exercises.
Of course, one of the best optimizations one can make is to replace references to local
variables with references to registers by allocating registers for holding local variable values.
We discuss register allocation in Chapter 7.
6.3.4 Low-Level Intermediate Representation (LIR)
The HIR lends itself to optimization but is not necessarily suitable for register allocation.
For this reason we translate it into a low-level intermediate representation (LIR) where
Phi functions are removed from the code and replaced by explicit moves, and
Instruction operands are expressed as explicit virtual registers.
For example, the LIR for Factorial.computeIter() is given below; notice that we retain
the control-flow graph from the HIR. Notice also that we have allocated virtual registers
to the computation. One may have an arbitrary number of virtual registers. In register
allocation, we shall map these virtual registers to actual physical registers on the MIPS
architecture. Because there might be many more virtual registers than physical registers,
the mapping may require that some physical registers be spilled to stack locations and
reloaded when the spilled values are needed again. Notice that each instruction is addressed
at a location that is a multiple of five; this leaves room for spills and loads (at intervening
locations).
computeIter(I)I
B0
B1
0:LDC[1][V32|I]
5:MOVE$a0[V33|I]
10:MOVE[V32|I][V34|I]
B2
15:LDC[0][V35|I]
20:BRANCH[LE][V33|I][V35|I]B4
B3
25:LDC[-1][V36|I]
30:ADD[V33|I][V36|I][V37|I]
35:MUL[V34|I][V33|I][V38|I]
40:MOVE[V38|I][V34|I]
45:MOVE[V37|I][V33|I]
50:BRANCHB2
B4
55:MOVE[V34|I]$v0
60:RETURN$v0