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6.2 SPIM and the MIPS Architecture
SPIM and the MIPS computer it simulates are both nicely described by SPIM's author
in [Larus, 2009]. Our brief description here is based on that.
6.2.1 MIPS Organization
The MIPS computer organization is sketched out in Figure 6.2.
FIGURE 6.2 The MIPS computer organization.
It has an integer central processing unit (CPU), which operates on thirty-two general-
purpose registers (numbered $0{$31); a separate oating- point coprocessor 1 (FPU), with
its own 32 registers ($f0{$f31) for doing single- precision (32-bit) and double- precision (64-
bit) floating point arithmetic, and coprocessor 0 for handling exceptions and interrupts, also
with its own set of registers, including a status register. There are instructions for moving
values from one register set to another. Our translation will focus on the integer-processing
unit; exercises may involve the reader's dealing with the other coprocessors.
Programming the raw MIPS computer can be quite complicated, given its (time) delayed
 
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