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Choosing the greatest partitioning is veri
ed by ILP algorithm. As result, we select
to implement the node 1 (permute C function) as hardware. Permute function (node)
is dominated by barrel shifter, integer arithmetic and logic decision. Implement it as
a hardware node allows the designer to minimize area and execution time at least to
1.95 % for LUTs resources and 0.86 % for execution time comparing to software
implementation. In addition, the integration of hardware nodes in soft-core Mi-
croBlaze processor did not require to inline assembler code because the FSL
interface has prede
ned C-macros that can be used for sending and receiving data
between hardware and software nodes. Results of s-Quark benchmark (illustrated
on the Table 8 ) prove that implementing complex applications on hardware/soft-
ware architecture with automatic hardware/software partitioning are better than
implementing these applications on software architectures (using MicroBlaze Soft-
core processors). As summary, Table 9 illustrates features of our design approach
compared to the existing ones.
8 Conclusions and Perspectives
FPGA presents an interesting circuit for implementing embedded applications. The
purpose of this chapter to illustrate the impact of co-design approach, on the design
acceleration and architecture performance. Based on the proposed co-design
approaches of hardware/software partitioning, we are contributing to speci
cation
in order to increase its level. We, also, added a step to select the
finest soft-core
processor con
guration in order
to facilitate the co-design process,
improve
embedded systems
performance and reduce design time.
The presented results demonstrate that the choice of the good con
'
guration has a
signi
cant impact on the system performance. The same approach can be used to
evaluate the performance of other embedded systems or other architectures. Design
methodologies of embedded systems, as mentioned in this paper, can be software,
hardware or both software/hardware. Using co-design methodology helps the
designer to obtain a good performance in a short time-to-market based on a good
hardware/software partition. In this chapter, we have also introduced the hardware/
software partitioning problem from a high-level speci
cation. Several partitioning
algorithms are presented in this study: One of them is based on ILP, which is used
in our empirical tests. The ILP algorithm works ef
ciently for graphs with several
hundreds of nodes and yield optimal solutions. As perspective, we can validate our
proposed approach for more complexes embedded applications using FPGA
devices for other vendors such as Altera, Actel, etc. We can also study the per-
formances and design time bene
ts using time estimation approach instead of real
performance evaluation.
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