Impact of Hardware/Software Partitioning and MicroBlaze FPGA Configurations on the Embedded Systems Performances - Complex System Modelling and Control Through Intelligent Soft Computations - page 724

Quark hash functions do not use huge values. They are dominated by barrel
shifter, integer arithmetic, logic decisions, and memory accesses intended to re ect

the CPU activities in computing applications. It takes a huge time for memory
access. As described in the Fig. 6 , selecting the best con

fl

guration enables a huge
gain perspective of execution time and area consumption. The performance of
implemented embedded systems using basic con g. 1) is very low

compared to the performance using Barrel Shifter Units (BS), Integer multiplier
(Mul) and Floating-Point Units (FPU) con

guration (con

guration (con g. 8). The execution time

using the basic con guration takes 29 mS (for u-Quark); 29.8 mS (for s-Quark) and

29.2 mS (for d-Quark). 8) takes 28.58 mS (for u-Quark); 29 mS (for s-Quark) and
28.84 mS (for d-Quark). Area consumption constraint has also an effect on the
embedded systems performance when modifying the con guration. Using basic

con g. 1), with optimization, takes 1,210 LUTs and 1,452 F-Fs.

However, using Barrel Shifter Units (BS), Integer multiplier (Mul) and Floating-
Point Units (FPU) con

guration (con

g. 8) takes 2,307 LUTs and 1,674 F-Fs. If the
application is area-critical, the user should select the best area/execution time
constraints. In real-time embedded systems, area consumption constraint is not very
important compared to the execution time.
Results prove that modifying con

guration (con

guration have an important effect on the
embedded system performances. These results are interesting to make an optimized
architecture for software design, designers of embedded systems can also benetof
FPGA hardware resources to more accelerate execution time and minimize the
energy consumption. Hardware/software architecture has to be used to satisfy
embedded systems constraints.
The results obtained from these different con gurations require approximately

20 min per con guration, so, 60 % of the time is spent by the synthesis to choose

the best con guration. Automate this step using time estimation approach allows

the acceleration of the design time. Also, area synthesis results can be used on the
designing of other embedded application, which reduce the design time.

7.2 Hardware/Software Partitioning

Partitioning an application among software solution on a soft-core processor (Mi-
croBlaze) and hardware co-processors (IPs) in on-chip con

gurable logic has been

shown to improve performance in embedded systems.
The used partitioning algorithm ILP is software oriented, because it starts with
only software nodes. For this reason, the initial speci cations were written in a

high-level language (C functions). These functions are divided into functional units
named nodes (node1, node2, node3 and node4 for Quark function). The

first step in
hardware/software partitioning step is the computation of both nodes and com-
munication (between hardware and software nodes) costs. The costs can be de ned

as the execution time and the resources using hardware implementation (Hw1) or
software implementation with different con

guration of Microblaze (Sw1 Sw17).

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