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Table 7 Temporal and Resources gain of s-Quark implementation
Task
1
2
3
4
Gain
Gt
Gr
Gt
Gr
Gt
Gr
Gt
Gr
G1
20.94
68
0.84
10
2.91
14
6.98
145
G2
18.94
88
0.67
18
2.66
23
6.18
148
G3
19.14
109
0.72
10
2.71
21
5.78
178
G4
18.74
118
0.71
12
2.7
20
6.58
187
G5
19.94
128
0.64
14
2.63
17
5.32
198
G6
20.94
130
0.72
13
2.71
21
3.08
197
G7
19.94
132
0.82
17
2.91
19
4.18
197
G8
19.34
136
0.74
15
1.73
23
6.18
199
G9
20.14
139
0.82
17
2.81
22
4.08
201
G10
21.81
143
0.72
18
2.71
20
6.73
206
G11
18.26
146
0.71
20
2.70
22
6.18
205
G12
21.14
140
0.70
23
2.69
21
4.08
197
G13
20.74
143
0.72
14
2.71
23
6.18
207
G14
19.14
136
0.66
26
2.65
26
4.08
185
G15
18.14
148
0.64
30
2.63
27
6.73
192
G16
17.59
151
0.7
29
2.69
28
7.18
195
G17
18.14
155
0.62
26
2.7
24
6.48
206
(1) Gt = Execution time before Hw migration
Execution time after Hw migration
−
(2) Gr = Resources before Hw migration
Resources after Hw migration
−
In the designing of Quark cryptographic application, the designer has to satisfy
temporal constraints while minimizing the number of the used resources. Parti-
tioning process is based on the assignment of tasks on software and hardware units.
This partitioning will be modi
ed, with new hardware/software assignments, until
the designer got the partition that meets the requirements of execution time and area
consumption. The interesting parameter for partitioning is the number of nodes,
which have to be partitioned. Using both hardware/software implementation, the
time taken to transfer data between the soft-core and IPs (or co-processors) will be
added. The cost of hardware/software communications are computed based on the
width of transmitted data (8, 16 or 32 bits) and the rate of the communication buses.
As seen above, Xilinx MicroBlaze soft-core processor implements Harvard
architecture. It means that it has separate bus interface for data and instruction
access. The OPB interface gives a connexion to both on- and off-chip peripherals
and memory. The MicroBlaze soft-core also provides 8 input and 8 output inter-
faces to Fast Simplex Link (FSL) buses. This FSL buses, 32 bits wide, are unidi-
rectional non-arbitrated dedicated communication channels. In our study, we used
the FSL interface due to its high performance (can reach up 300 Mb/S). EDK
provides a set of Macros for reading and writing to or from FSL interface. Our
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