Impact of Hardware/Software Partitioning and MicroBlaze FPGA Configurations on the Embedded Systems Performances - Complex System Modelling and Control Through Intelligent Soft Computations - page 720

6.2 Application of the Proposed Design Approach
for Quark Benchmark

6.2.1 Effect of MicroBlaze Soft-Core Con guration

on Embedded Systems Performance

For embedded application, different MicroBlaze con gurations can be provided. In

real-time complex applications, both execution time and area consumption deter-
mine the ef ciency and the high performance of the con gured embedded soft-core

processor.
The evaluation of hardware area presents one of the metric to select embedded
con

gurations, which requires an optimal area. In a software design methodology,
area consumption is independent from the implemented application. We can
evaluate the performance of the soft-core processor for each con guration directly

after the hardware speci cation step. Results prove that the average number of

slices (a group of logic cell resources in FPGA) without using optimization option
is very important. Table 6 depicts the area consumption recorded for some possible
MicroBlaze con

gurations.
To evaluate the performance of the MicroBlaze soft-core processor, we have
estimated the execution time in order to choose the most ef guration,

which takes the minimum execution time onto the smaller hardware area. In our
work, we compute the execution time of the con

cient con

guration described in the table for
three Quark hash functions (u-Quark function, d-Quark function and s-Quark
function). Figure 7 illustrates the Quark hash functions execution time measurement
for the 17 con gurations of Xilinx MicroBlaze.

6.2.2 Automation of Partitioning Process

Designers have to specify the target architecture early in the design by de ning the

con guration of the software nodes to synthesize hardware nodes. Moreover,

designers have, also, to determine the design constraints, performance constraints
(timing) and resource constraints (area, memory). In this study, we choose to
evaluate the proposed approach for a lightweight cryptographic s-Quark bench-
mark. We divide the C-high-level speci

cation into four functional units (C func-
tions) presented as nodes. We compute than nodes costs for all hardware and
software possible architecture. For Software nodes, cost computation will be
assured by pro ling. For Hardware nodes, C functions will be transformed into

Hardware speci cation using HLS approach, synthesized and analysed using

Logical synthesis to get its costs. We propose MicroBlaze soft-core as software
architecture with its different con

gurations (presented above). With our approach;
we have to specify the costs (execution time and resources utilization) for each
s-Quark node which can be implemented using soft-core (within all con gurations).