Information Technology Reference
In-Depth Information
Therefore, Partitioning is a well-known problem. During the last years, many
partitioning approaches have been proposed to automate the partitioning process
decision of hardware and software components (De Michell and Gupta
1997
;
Wiangtong et al.
2005
). The feasibility of these approaches depends essentially on
the system-level speci
cation, the target architecture and the constraints parameters
(hardware size, power consumption, execution time, computation, etc.). Several
works were focused on the automation of the hardware/software partitioning using
co-design methodologies. Many interesting approaches are presented. Some of
them are described on Table
2
.
As described in the table above, many partitioning hardware/software approa-
ches exist (Madsen et al.
1997
;Bo
ung et al.
1999
; Chatha and Vemuri
2000
).
From the many co-design approaches, we will examine some of these. A hardware/
software partitioning approach is proposed by Lysecky and Vahid (
2004
). This
approach uses a relaxed cost function to satisfy performance in an Integer Linear
Programing (ILP); it handles hardware minimization in an outer loop. Lysecky and
Vahid (
2004
), presents a binary constraint search algorithm which determines the
smaller size constraint. Vahid partitioning approach minimizes hardware, but not
execution time. Kalavade and Lee (
1994
), proposed also a different hardware/
software partitioning approach. It is based on GCLP algorithm to determine for
each node iteratively the mapping to hardware or software. The used GCLP
algorithm selects its appropriate objective according to critical time measure and
another measure for local optimum.
ß
Table 2 Hardware/software partitioning approaches
Approaches
Cosyma
Vulcan
Polis
CoWave
GrapeII
Speci
cation
SDL
language
HardwareC
FSM,
esterel
DFL, C, etc.
DFL
Internal model
No
No
Yes
Yes
Yes
Support Y chart
model?
No, Semi-
automatic
Yes, with
migration
No,
manual
No
Yes
Support automating
partitioning?
No
No
Yes
(Y-chart
like)
No
Yes
(Y-chart
like)
Supports the explo-
ration of the design
space?
Low
Low
Very
high
High
Medium
Level specification
of approach
No
No
Yes
No
No
Support for
synthesis
No
No
Yes
No
Yes
Target architecture
Mono-proces-
sor: CPU + Co-
processor
Mono-processor:
CPU + ASIC with
buses
Mono-
processor
Multi-pro-
cessors with
ASICs
Multi-pro-
cessors with
FPGAs
Search WWH ::
Custom Search