Impact of Hardware/Software Partitioning and MicroBlaze FPGA Configurations on the Embedded Systems Performances - Complex System Modelling and Control Through Intelligent Soft Computations - page 698

(Fujita and Nakamura 2001 ) and Bluespec (Dave et al. 2005 ; Gruian and Westmijze
2008 ; Talpin et al. 2003 ). Second, there is Hardware In the Loop (HIL) technique
which increase the tractability and earlier testability of the design product (Wash-
ington and Dolman 2010 ). The automation of the hardware/software partitioning
step on the co-design methodologies using low-level speci

cation presents the third

approach (Stitt et al. 2003 ).
Other designers have based their methodologies on minimizing the design com-
plexities. One approach is the use of Intellectual Proprieties (IPs) blocs and cores
(Mcloone and Mccanny 2003 ) provided by vendors or designers (Lach et al. 1999 ).
An other is the automating of the hardware code generation HDL (Hardware
Description Language) from a high level speci cation (Samarawickrama et al. 2010 ;

Ku andDeMitcheli 1992 ). This speci cation can be de ned as language (C, SystemC,

etc.) or models (Matlab, Sycos etc.) or UML (Uni ed Modeling Language) diagrams,

called HLS (High Level Synthesis) approach (Lingbo et al. 2006 ; Wakabayashi and
Okamoto 2000 ).
During last decades, early designers works have been focused on new contri-

butions of the existing design methodologies, which allow both the high level
speci

'

cation and the automation of the design process to decrease the systems
complexities, reduce the development time to enlarge the time reserved to the
optimization and increase their performance. None of these approaches deals with
the impact of the best configuration selection of soft-cores processors performance
in terms of computation acceleration.
The goal of this chapter is to actively contribute to the existing co-design
approaches including hardware/software partitioning step using high level specifi- -

cation. The chapter also aims at adding a step to the selection f the best soft-cores
processors con

guration. These contributions permit the increase of embedded
systems performance (soft-cores computation) and the reduction of systems com-
plexities. The remaining parts of this paper are organized as follows: Sect. 2
illustrates the related works and background of design methodologies. Section 3
presents the MicroBlaze soft-core processor. Section 4 depicts our co-design
approach. Section 4 presents the performance evaluation techniques and the
lightweight cryptographic algorithm. Section 5 determines results of our co-design
approach. In Sect. 6 , we will discuss results. Finally, Sect. 7 summarizes our study,
and gives our perspectives.

2 Related Works and Background

In this section, the different steps of design methodologies will be presented in
reverse. We will begin by de

ning the different architecture of implementation. We
will proceed with the design methodologies approaches speci cally HLS approach

and hardware/software partitioning approach. Finally, system level speci cation of

embedded systems will be dealt with.