Approximation of Optimized Fuzzy Logic Controller for Shunt Active Power Filter - Complex System Modelling and Control Through Intelligent Soft Computations - page 573

Table 2 System parameters

System parameter Value

Source voltage (V s ) 230 V (rms/phase)

System frequency (f) 50 Hz

Source impedance (R s ,L s ) 0.1 ʩ , 0.5 mH

0.4 ʩ , 3.35 mH

Filter impedance (R F ,L F )

Reference DC link voltage (V dc, ref ) 680 V

DC link capacitance (C dc ) 2,000 ʼ F

Performance analysis of shunt APF using 49-rule FLCs with different MFs and
approximated FLC using optimized MFs is presented in next section.

4 Simulation Results

Using the system parameters given in Table 2 , simulation results of shunt APF with
49-rule FLC using different MFs are compared to

find the optimized membership
function. Simulations are performed on MATLAB/Simulink, using same normali-
zation and de-normalization factors for all the MFs.
The performance of shunt APF is analyzed for the three randomly varying
loading conditions. Initially, the filter is switched on at 0.05 s, to compensate the

current harmonics injected by a non-linear load. The load is varied in three steps,
each of 10 cycles (i.e., 0.2 s), discussed as three different cases, i.e., Case-1, Case-2,
and Case-3, in following subsections. The waveforms during switch-on as well as
during load perturbation are shown in Figs. 12 , 13 , 14 and 15 , for triangular, Gbell,
Gaussian, and Dsig MFs, respectively.

4.1 Case-1: Switch-On Response

During switch-on at 0.05 s, the recti er fed load consists of a resistance and

inductance of 30 and 20 mH, respectively. The comparison of dynamic perfor-

mance reveals that the peak overshoot in DC link voltage is 1.32 % with triangular
MFs as compared to 0.51 % with Gaussian and 0.05 % with Dsig MFs, respec-
tively. The response of Gbell MFs is not found to maintain the dc link voltage at
reference level as depicted in Fig. 13 . The switch on response with Dsig MFs with
minimum overshoot suffers from steady state error in regulating the dc link voltage.
The settling time of dc link voltage within

ʩ

± 1 % of reference value is least with

Gaussian MFs, as represented in Table 3 .
The THD pro le for each cycle, after switch-on, is presented in Fig. 16 , All the

controllers are found capable to bring the THD of source current well within the
limits (5 %) imposed by IEEE-519 ( 1993 ), just in the very next cycle of switching