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In-Depth Information
Current Control Loop
I sa
I sb
I sc
Hysteresis current
controller and Gate
pulse generation
V dc
V dc,ref
V sa
V sb
V sc
C dc
Shunt APF
Gate pulses
_
+
Unit sinusoidal
signal generation
I * sa
I * sb
I * sc
Multiplier and
reference current
generator
I max
Voltage control Loop
Fig. 4 Block diagram of current control loop of FLC based shunt APF
and sensed actual currents (i sa ;
i sc ) are compared in hysteresis current controller
to generate the switching signals for converter devices.
The switching signals of any phase (say phase
i sb ;
'
a
'
) are obtained using following
methodology:
If i sa [
, the upper switch of
i sa þ
hb
first arm of converter is on and lower
, the upper switch of
i sa þ
switch is off and if if sa \
hb
first arm of converter is off
and lower switch is on, where
is the hysteresis band on either side around the
reference current. Similarly, switching patterns for other two phases are also
obtained. In this way, source currents and DC link voltage are regulated to follow
their corresponding reference signals. The source currents become sinusoidal and in
phase with respective phase voltages to achieve the objective of ef
'
hb
'
cient harmonic
and reactive power compensation.
Using hysteresis current control, the source currents are forced to follow the
sinusoidal reference current of corresponding phase, within a
fixed hysteresis band.
The width of hysteresis window determines the source current pattern, its harmonic
spectrum and switching frequency of the devices. The reference source currents for
three different phase a, b, and c can be given as:
i sa ¼
i smax sin x
t
2 3 Þ
i sb ¼
i smax sin ðx
t
ð 3 Þ
2
3 Þ
i sc ¼
i smax sin ðx
t
þ
As this chapter basically deals with control technique using FLC, next section
provides an insight into basic structure of FLC, design of rule-base, different
membership functions, etc. This section also discuss the proposed approximation
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