Global Positioning System Reference
In-Depth Information
With the code setter hardware described earlier, the C/A code setup process
works as follows. In accordance with a future time delay equal to a fixed number of
code NCO reference clock cycles later, the code accumulator value for that future
time is loaded into the code setter. This value matches the desired C/A code time
after the scheduled time delay. The value for the code setter is computed just as if the
1,023 state C/A code generator had the same linear counting properties as a 1,023
bit counter. The code setter begins counting after the scheduled time delay, starting
with the loaded count value. The code setter sets the G1 and G2 registers when the
count rolls over. If the value sent from the code accumulator was greater than 511,
the C/A code setter resets the G1 and G2 registers to their initial states. If the value
sent from the code accumulator was less than or equal to 511, the code setter sets the
G1 and G2 registers to their halfway points. As a result, the C/A replica code genera-
tor phase state matches the code accumulator GPS time state when the code setter
rolls over and is synchronized to the code accumulator thereafter. When the receiver
is tracking the SV after initialization, the code setter process can be repeated as often
as desired without altering the C/A replica code generator phase state, because both
the code accumulator and the code generator are ultimately synchronized by the
same reference clock, the code NCO clock. If the receiver is in the search process, the
C/A code advance/retard feature shown in Figure 5.31 provides the capability to add
or remove clock cycles in half-chip increments. The code accumulator must keep
track of these commanded changes. If the receiver can predict the satellite transmit
time to within a few chips during the search process, it can use the code setter to per-
form a direct C/A code search. This condition is satisfied if the receiver has previ-
ously acquired four or more satellites and its navigation solution has converged.
Ordinarily, all 1,023 C/A code chips are searched.
Some commercial C/A code receiver designs do not use a code NCO, but instead
propagate the code generator at the nominal spreading code chip rate between code
loop updates, tolerating the error build up due to code Doppler and ionospheric
delay changes. Instead of the code NCO, a counter with a fractional chip
advance/retard capability is used to adjust the phase of the C/A replica code genera-
tor in coarse phase increments. This results in a very low-resolution code measure-
ment
(large
quantization
noise)
and
a
noisy
pseudorange
measurement
in
comparison to the code NCO technique.
The algorithm for the code accumulator output to the C/A code setter is as fol-
lows:
[
]
{
}
[
]
(
)
G
=
remainder of
whole part of
X
1 10
1023
,
(5.31)
where:
G
=
future scheduled C/A code time value sent to the code setter
X
1
=
future scheduled GPS time of week in P chips (0
≤
X
1
≤
15,344,999)
An alternative design to the code setter timing technique is to precompute and
store all 1,023 10-bit PRN states for G1 and G2 in two tables, then use the value G
from (5.31) as the index to these tables. This would result in two 10-bit words being
transferred into a G1 buffer register and a G2 buffer register. At the instance of the
Search WWH ::
Custom Search