Satellite Signal Acquisition, Tracking, and Data Demodulation - Understanding GPS: Principles and Applications - page 205

dump times and the updates to the code and carrier NCOs are performed on a
changing skewed time phase with respect to the FTF time phase, but the receiver
baseband process learns and controls this time skew in discrete phase increments.
The code accumulator is normally updated on the skewed time schedule that
matches the code NCO update schedule. Therefore, if all of the GPS receiver mea-
surements of a multiple channel GPS receiver are to be made on the same FTF, the
contents of the code accumulator, when extracted for purposes of obtaining a mea-
surement, must be propagated forward by the amount of the time skew between the
code NCO update events and the FTF.

5.7.1.3 Maintaining the Code Accumulator
Although there are many code accumulator time-keeping conventions that would
work, the following convention is convenient for setting the initial code generator
and NCO phase states [1]. Three counters, Z, X1, and P, are maintained as the code
accumulator. The Z counter (19 bits) accumulates in GPS time increments of 1.5
seconds, then is reset one count short of the maximum Z count of 1 week 403,200.

Hence, the maximum Z count is 403,199. The X1 counter (24 bits) accumulates in
GPS time increments of integer P chips, then is reset one count short of the maxi-
mum X1 count of 1.5 seconds

=

15,345,000. Hence, the maximum X1 count is
15,344,999. The P counter accumulates in GPS time increments of fractions of a P
chip, then rolls over one count short of one P chip. The P counter is the same length
as the code NCO adder. A typical length is 32 bits.
Note in Figure 5.13 that the code NCO synthesizes a code clock rate that is an
integer multiple, 2/ D , faster than the code generator spreading code chip rate,
where D is the E-L code correlator spacing in chips (often D

=

1). This is required in
order to generate phase shifted replica codes, which are necessary for error detec-
tion in the code discriminator. The P counter tracks the fractional part of the code
phase state, which is the code NCO state. Using this convention and assuming that
the code NCO and code accumulator are updated every T seconds, the algorithm
for maintaining the code accumulator is as follows. Note that the equals sign means
“is replaced with.”

=

P temp = Pf +∆φ T

c co

P = fractional part of P temp (chips)

X temp = ( X 1 + whole part of P temp )/15,345,000

X 1 = remainder of X temp (chips)

Z = remainder of [( Z + whole part of X temp )/403,200] (1.5 seconds) (5.28)

where:

P temp = temporary P register

f C = code NCO clock frequency (Hz)

∆φ CO = code NCO phase increment per clock cycle

= code NCO bias + code loop filter velocity correction

T = time between code NCO updates (seconds)