Global Positioning System Reference
In-Depth Information
1.023 Mchip/s rate
1,023 chip period=1msperiod
G1(t)
C/A code
Gi(t) = G1(t)
G1 Generator
G2(t + di Tg)
1.023 MHz
X1 epoch
Satellite i
Delay
di Tg
.
G2 Generator
G2(t)
10.23 Mchips/s rate
15,345,000 chip period = 1.5 sec period
÷ 10
X1 epoch
X1(t)
P Code
Pi(t) = X1(t)
X1 generator
Clock
10.23 MHz
X2(t+iTp)
10.23 MHz
X1 epoch
Satellite i
X2(t )
Delay
iTp
X2 generator
10.23 Mchips/s rate
15,345,037 chip period
37 chips longer than X1(t)
Figure 4.9
GPS code generators.
the C/A-code and P-code generator shift registers are summarized in Table 4.4. The
unique C/A code for each SV is the result of the exclusive-or of the G1 direct output
sequence and a delayed version of the G2 direct output sequence. The equivalent
delay effect in the G2 PRN code is obtained by the exclusive-or of the selected posi-
tions of the two taps whose output is called G21. This is because a maximum-length
PRN code sequence has the property that adding a phase-shifted version of itself
produces the same sequence but at a different phase. The function of the two taps on
the G2 shift register in Figure 4.10 is to shift the code phase in G2 with respect to the
code phase in G1 without the need for an additional shift register to perform this
delay. Each C/A code PRN number is associated with the two tap positions on G2.
Table 4.3 describes these tap combinations for all defined GPS PRN numbers and
specifies the equivalent direct sequence delay in C/A code chips. The first 32 of these
PRN numbers are reserved for the space segment. Five additional PRN numbers,
PRN 33 to PRN 37, are reserved for other uses, such as ground transmitters (also
referred to as pseudosatellites or pseudolites ). Pseudolites were used during Phase I
(concept demonstration phase) of GPS to validate the operation and accuracy of the
system before any satellites were launched and in combination with the earliest sat-
ellites. C/A codes 34 and 37 are identical.
The GPS P code is a PRN sequence generated using four 12-bit shift registers
designated X1A, X1B, X2A, and X2B. A detailed block diagram of this shift register
architecture is shown in Figure 4.11 [10]. Not included in this diagram are the con-
trols necessary to set or read the phase states of the registers and counters. Note that
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