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3. Consider the binary numbers in the following addition and subtraction pro-
blems to be signed 6-bit values in the 2's complement representation. Per-
form each of the following operations, specifying whether overflow occurs.
010110
011001
110111
100001
111111
011010
þ
001001
þ
010000
þ
101011
2
011101
2
000111
2
100010
4. Multiply each of the following pairs of signed 2's complement numbers
using the 2-bit Booth algorithm.
M
¼
010111 M
¼
110011 M
¼
110101 M
¼
1111
Q
¼
110110
Q
¼
101100
Q
¼
011011
Q
¼
1111
5. Divide each of the following pairs of signed 2
0
s complement numbers using
both the restoring and the nonrestoring algorithms.
X
¼
010111
X
¼
110011
X
¼
110101
X
¼
1111
D
¼
110110
D
¼
101100
D
¼
011011
D
¼
1111
6. Show how to perform addition, subtraction, multiplication, and division of
the following floating numbers.
A
¼
0
10001
011011
B
¼
1
01111
101010
The numbers are represented in a 12-bit format using a base b
¼
2, a 5-bit
16, and 6-bit normalized mantissa m.
7. Show a complete design (in terms of the logic equations) for a 4-bit adder
exponent e with a bias
¼
/
subtractor using carry-look-ahead technique for all carries
c
1
, c
2
, c
3
, c
4
.
Assume that
the two 4-bit
input numbers are A
¼
a
4
a
3
a
2
a
1
and
B
¼
b
4
b
3
b
2
b
1
.
8. Design a BCD adder using a 4-bit binary adder and the least number of logic
gates. The adder should receive two 4-bit numbers A and B and should pro-
duce 4-bit sum and a carry output.
9. Show a design of a 16-bit CLA that uses the 4-bit CLA block shown in
Figure 4.5. Compute the delay and the area (in terms of the number of
logic gates required).
10. Compare the longest path delay from input to output of a 32-bit adder using
4-bit CLA adder blocks in a multilevel architecture with that of a 32-bit CRT
adder. Assume that a gate delay is given by T
g
.
11. Convert each of the following decimal numbers to their IEEE single-
precision floating-point counterparts.
(a)
76
(b) 0.92
(c) 5.3125
2
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