Computer Arithmetic - Fundamentals of Computer Organization and Architecture - page 78

Exponent E2 Exponent E1 Mantissa M2 Mantissa M1

Subtract Divide

Result normalization and round logic

Result Exponent Result Mantissa

Figure 4.15 FP division

In the single-precision format, base 2 is used, thus allowing the use of a hidden
bit. The exponent field is 8 bits. The IEEE single-precision representation is shown
in Figure 4.16.
The 8-bit exponent allows for any of 256 combinations. Among these, two com-
binations are reserved for special values:

1. e ¼ 0 is reserved for zero (with fraction m ¼ 0) and denormalized numbers

(with fraction m = 0).

2. e ¼ 255 is reserved for

+ 1

(with fraction m ¼ 0) and not a number (NaN)

(with fraction m = 0).

m ¼ 0 m = 0

e ¼ 0 0 Denormalized

e ¼ 255

+ 1

NaN

The single extended IEEE format extends the exponent field from 8 to 11 bits and
the mantissa field from 23 1 to 32 or more bits (without a hidden bit). This results in

a total length of at least 44 bits. The single extended format is used in calculating
intermediate results.

þ

4.3.4. Double-Precision IEEE Format

Here the exponent field is 11 bits and the significant field is 52 bits. The format is
shown in Figure 4.17.
Similar to the single-precision format, the extreme values of e (0 and 2047) are
reserved for the same purpose.

Figure 4.16 IEEE single-precision representation