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given operation is outside the range of the representable numbers. Consider the fol-
lowing two examples.
Example
Consider adding the two 2's complement numbers (
þ
7) and (
þ
6). The
addition can be done as (
þ
7)
þ
(
þ
6)
¼
þ
13, that is, 0111
þ
(0110)
1101, a
¼
wrong result. This is because the result exceeds the largest value (
þ
7).
Example
Consider adding the two 2's complement numbers (
7) and (
4). The
2
2
addition can be done as (
0101, a
wrong result. This is because the result is less than the smallest value (
7)
þ
(
4)
11, that is, 1001
þ
(1100)
2
2
¼ 2
¼
8).
2
Notice that the original numbers are negative while the result is positive.
From these two examples, we can make the following observation: when two
numbers (both positive or both negative) are added, then overflow can be detected
if and only if the result has an opposite sign to the added numbers.
Subtraction
In 2's complement, subtraction can be performed in the same way
addition is performed. For example, to perform B
A
¼
B
þ
A
þ
1, that is, sub-
tracting A from B is the same as addition to the complement of A to B.
Example
Consider the subtraction 2
2
7
¼ 2
5. This can be performed as
2
þ
¯
þ
1
¼
0010
þ
1000
þ
0001
¼
1011 (
2
5).
It should be noted that our earlier observation about the occurrence of overflow in
the context of addition applies in the case of subtraction as well. This is because sub-
traction is after all addition to the complement. Consider the following illustrative
example.
Example
Consider the subtraction 7
(
7)
14. This can be performed as
2
2
¼
¯
7
þ
þ
1
0111
þ
1000
þ
0001
(1) 0000, a wrong answer (result
7).
¼
¼
.
Hardware Structures for Addition and Subtraction of Signed
Numbers
The addition of two n-bit numbers A and B requires a basic hardware
circuit that accepts three inputs, that is, a
i
, b
i
, and c
i
1
. These three bits represent
respectively the two current bits of the numbers A and B (at position i) and the
carry bit from the previous bit position (at position i
2
1). The circuit should pro-
duce two outputs, that is, s
i
and c
i
representing respectively the sum and the
carry, according to the following truth-table.
a
i
0
0
0
0
1
1
1
1
b
i
0
0
1
1
0
0
1
1
c
i
2
1
0
1
0
1
0
1
0
1
s
i
0
1
1
0
1
0
0
1
c
i
0
0
0
1
0
1
1
1
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