Instruction Set Architecture and Design - Fundamentals of Computer Organization and Architecture - page 23

2.2.4. Indexed Mode

In this addressing mode, the address of the operand is obtained by adding a con-
stant to the content of a register, called the index register. Consider, for example,
the instruction LOAD X(R ind ), R i . This instruction loads register R i with the contents
of the memory location whose address is the sum of the contents of register
R ind and the value X. Index addressing is indicated in the instruction by including
the name of the index register in parentheses and using the symbol X to indicate
the constant to be added. Figure 2.8 illustrates indexed addressing. As can be
seen, indexing requires an additional level of complexity over register indirect
addressing.

2.2.5. Other Modes

The addressing modes presented above represent the most commonly used modes in
most processors. They provide the programmer with sufficient means to handle most
general programming tasks. However, a number of other addressing modes have
been used in a number of processors to facilitate execution of specific programming
tasks. These additional addressing modes are more involved as compared to those
presented above. Among these addressing modes the relative, autoincrement, and
the autodecrement modes represent the most well-known ones. These are explained
below.

Relative Mode Recall that in indexed addressing, an index register, R ind , is used.

Relative addressing is the same as indexed addressing except that the program
counter (PC) replaces the index register. For example, the instruction LOAD X(PC),
R i loads register R i with the contents of the memory location whose address
is the sum of the contents of the program counter (PC) and the value X. Figure 2.9
illustrates the relative addressing mode.

Autoincrement Mode This addressing mode is similar to the register indirect

addressing mode in the sense that the effective address of the operand is the content
of a register, call it the autoincrement register, that is included in the instruction.

Operation Value X

Memory

+

Index Register ( R ind ) operand

Figure 2.8 Illustration of the indexed addressing mode