Instruction Set Architecture and Design - Fundamentals of Computer Organization and Architecture - page 18

Figure 2.3 Illustration of the memory read operation

Figure 2.3 illustrates the operation of reading the word stored in the memory
location whose address is 2010. Part a of the figure shows the status of the registers
and memory locations involved in the read operation before the execution of the
operation. Part b of the figure shows the status after the read operation.

2.2. ADDRESSING MODES

Information involved in any operation performed by the CPU needs to be addressed.
In computer terminology, such information is called the operand. Therefore, any
instruction issued by the processor must carry at least two types of information.
These are the operation to be performed, encoded in what is called the op-code
field, and the address information of the operand on which the operation is to be
performed, encoded in what is called the address field.
Instructions can be classified based on the number of operands as: three-address,
two-address, one-and-half-address, one-address, and zero-address. We explain
these classes together with simple examples in the following paragraphs. It should
be noted that in presenting these examples, we would use the convention operation,
source, destination to express any instruction. In that convention, operation rep-
resents the operation to be performed, for example, add, subtract, write,orread.
The source field represents the source operand(s). The source operand can be a con-
stant, a value stored in a register, or a value stored in the memory. The destination
field represents the place where the result of the operation is to be stored, for
example, a register or a memory location.
A three-address instruction takes the form operation add-1, add-2, add-3. In this
form, each of add-1, add-2, and add-3 refers to a register or to a memory location.
Consider, for example, the instruction ADD R 1 ,R 2 ,R 3 . This instruction indicates that