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11.6. ANALYSIS AND PERFORMANCE METRICS
Having provided an introduction to the architecture of multiprocessors, we now pro-
vide some basic ideas about the performance issues in multiprocessors. Interested
readers are referred to Chapter 3 of our topic on Advanced Computer Architecture
and Parallel Processing (see reference list) (Volume II) for more details.
A fundamental question that is usually asked is how much faster a given problem
can be solved using multiprocessors as compared to a single processor? This
question can be formulated into the speed-up factor defined below.
S(n)
¼
speed-up factor
¼
Increase in speed due to the use of a multiprocessor system consisting of
n processors
Execution time using a single processor
Execution time using n processors
¼
A related question is that how efficiently each of the n processors is utilized. The
question can be formulated into the efficiency defined below.
E(n)
¼
Efficiency
S(n)
n
¼
100%
In executing tasks (programs) using a multiprocessor, it may be assumed that a
given task can be divided into n equal subtasks each of which can be executed by
one processor. Therefore, the expected speed-up will be given by the S(n) ¼ n
while the efficiency E(n) ¼
100%. The assumption that a given task can be
divided into n equal subtasks, each executed by a processor, is unrealistic. In
Chapter 3 of our topic on Advanced Computer Architecture and Parallel Processing
(see reference list) meaningful computation models will be developed and analyzed.
A number of other performance metrics are also introduced and analyzed in the same
chapter.
11.7. SUMMARY
In this chapter, we have navigated through a number of concepts and system
configurations related to the issues of multiprocessing. In particular, we have
provided the general concepts and terminology used in the context of multiproces-
sors. A number of taxonomies for multiprocessors have been introduced and
analyzed. Two memory organization schemes have been introduced. These are
the shared-memory and message-passing systems. In addition, we have introduced
the different topologies used for interconnecting multiple processors. In Chapter 2
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