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2
5
6
5
1
8
5
Type
DST
Op-Code
SRC 1
0
FP-OP
SRC 2
Type
DST
Op-Code
SRC 1
1
Immediate Constant
Figure 10.2 Three operand instructions formats used in RISC
3. Branch & Call: JMPX COND,(R x )S; PC R x þ S;whereCOND is a condition
4. Special Instructions: GETPSW R d ; R d PSW
All arithmetic and logical instructions have three operands and have the form Desti-
nation :
¼ source1 op source2 (Fig. 10.2). The LOAD and STORE instructions may use
either of the indicated formats with DST being the register to be loaded or stored. The
low order 19 bits of the instructions are used to determine the effective address.
Instructions load and store 8-, 16-, 32-, and 64-bit quantities into 32-bit registers.
Two methods are provided for calling procedures. The CALL instruction uses a
30-bit PC relative offset (Fig. 10.3).
The JMP instruction uses any of the instruction formats used for arithmetic and
logical operations and allows the return address to be put in any register.
RISC uses a three-address instruction format with the availability of some two-
and one-address instructions. There are only two addressing modes. These are
indexed mode and PC relative modes. The indexed mode can be used to synthesize
three other modes. These are base-absolute (direct), register indirect, and indexed
for linear byte array modes. RISC uses a static two-stage pipeline: fetch and execute.
The floating-point unit (FPU) contains thirty-two 32-bit registers to hold 32 single
precision (32-bit) floating-point operands, 16 double-precision (64-bit) operands, or
eight extended-precision (128-bit) operands. The FPU can execute about 20 float-
ing-point instructions most of them in single-, double-, or extended-precision using
the first instruction format used for arithmetic. In addition to instructions for loading
and storing FPUs registers, the CPU can also test FPUs registers and branch con-
ditionally on results. RISC employs a conventional MMU supporting a single
paged 32-bit address space. The RISC four-bus organization is shown in Figure 10.4.
10.5.2. Stanford MIPS (Microprocessor Without Interlock
Pipe Stages)
MIPS is a 32-bit pipelined LOAD
STORE machine. It uses a five-stage pipeline
consisting of Instruction Fetch (IF), Instruction Decode (ID), Operand Decode
/
2
30
Type
PC-Relative Displacement
Figure 10.3 Procedure call instruction in RISC
 
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