Reduced Instruction Set Computers (RISCs) - Fundamentals of Computer Organization and Architecture - page 223

TABLE 10.5 Summary of Features of a Number of RISC and a CISC

Motorola
88110

Alpha AXP
21264

Power
PC 601 Pentium

Company Motorola Compaq (DEC) Intel IBM

Architecture RISC RISC CISC RISC

# Registers(I) 32 80 64 32

Cache I / D 8 / 8KB 64 / 64 KB 8 / 8KB 32

# Registers (GP / FP) 32 / 32 31 / 31 8 / 8 32 / 32

# Inst / cycle 2 1 2 3

# Pipelines (I / FP) NS 4 / 2 5 / 8 4 / 6

Multiprocessing Support No Yes Yes Yes

6. Pipelined instruction execution
7. Large number of general-purpose registers or the use of advanced compiler
technology to optimize register usage
8. One instruction per clock cycle
9. Hardwired control unit design rather than microprogramming

10.5. PIONEER (UNIVERSITY) RISC MACHINES

In this section, we present brief descriptions of the main architectural features of two
pioneer university-introduced RISC machines. The first machine is the Berkeley
RISC and the second is the Stanford MIPS machine. These machines are presented
as a means to show how original RISC machines look and also to make the reader
appreciate the advances made in RISC machines development since their inception.

10.5.1. The Berkeley RISC

There are two Berkeley RISC machines: RISC-I and RISC-II. Unless otherwise
mentioned, we refer to RISC-I in our discussion. RISC is a 32-bit LOAD STORE

architecture. There are 138 32-bit registers R 0 -R 137 available to the users. The
first ten registers R 0 -R 9 are global registers (seen by all procedures). Register R 0
is used to synthesize addressing modes and operations that are not directly available
on the machine. Registers R 10 -R 137 are divided into an overlapping register window
scheme with 32 registers visible at any instant. A 5-bit variable, called current
window pointer (CWP) is used to point to the current register set.
All RISC instructions occupy a full word (32 bits). The RISC instruction set is
divided into four categories. These are ALU (a total of 12 instructions), Load

/

Store
(a total of 16 instructions), Branch & Call (a total of seven instructions), and special
instructions (a total of four instructions). Some examples of the RISC instructions are:

/

1. ALU: ADD R s , S, R d ; R d R s þ S
2. Load / Store: LDXW (R x )S, R d ; R d M[R x þ S]