Reduced Instruction Set Computers (RISCs) - Fundamentals of Computer Organization and Architecture - page 221

TABLE 10.2 Different Register Windows Characteristics

Number of
windows

Number of registers
per window Architecture

Berkeley RISC-I 8 16

Pyramids 16 32

SPARC 32 32

In addition, a set of a fixed number of CPU registers are identified as global reg-
isters and are available to all procedures. For example, references to registers
0 through 7 in the SPARC architecture refer to unique global registers, and refer-
ences to registers 8 through 31 indicate registers in the current window. The current
window is pointed to using what is normally called the current window pointer
(CWP). Upon having all windows filled, the register window wraps around, thus
acting like a “circular buffer.” Table 10.2 shows the number of windows and the
window size for a number of architectures.
It should be noted that a study was conducted in 1985 to find out the impact of
using register window on the performance of the Berkeley RISC. In this study,
two versions of the machine were studied. The first is designed with register win-
dows and the second was a hypothetical Berkeley RISC implemented without win-
dows. The results of the study indicated a decrease by a factor of 2 to 4 (depending
on specific benchmark) in the memory traffic due to the use of register windows.

10.4. RISCs VERSUS CISCs

The choice of RISC versus CISC depends totally on the factors that must be con-
sidered by a computer designer. These factors include size, complexity, and
speed. A RISC architecture has to execute more instructions to perform the same
function performed by a CISC architecture. To compensate for this drawback,
RISC architectures must use the chip area saved by not using complex instruction
decoders in providing a large number of CPU registers, additional execution
units, and instruction caches. The use of these resources leads to a reduction in
the traffic between the processor and the memory. On the other hand, a CISC archi-
tecture with a richer and more complex instructions, will require a smaller number of
instructions than its RISC counterpart. However, a CISC architecture requires a
complex decoding scheme and hence is subject to logic delays. It is therefore reason-
able to consider that the RISC and CISC paradigms differ primarily in the strategy
used to trade off different design factors.
There is very little reason to believe that an idea that improves performance for a
RISC architecture will fail to do the same thing in a CISC architecture and vice
versa. For example, one key issue in RISC development is the use of optimizing
the compiler to reduce the complexity of the hardware and to optimize the use of
CPU registers. These same ideas should be applicable to CISC compilers. Increasing