Reduced Instruction Set Computers (RISCs) - Fundamentals of Computer Organization and Architecture - page 217

& CHAPTER 10

Reduced Instruction Set
Computers (RISCs)

This chapter is dedicated to a study of reduced instruction set computers (RISCs).
These machines represent a noticeable shift in computer architecture paradigm.
This paradigm promotes simplicity rather than complexity. The RISC approach is sub-
stantiated by a number of studies indicating that assignment statements, conditional
branching, and procedure calls

return represent more than 90% and that complex
operations such as long division represent only about 2% of the operations performed
in a typical set of benchmark programs. These studies showed also that among all
operations, procedure calls

/

return are the most time-consuming. Based on such
results, the RISC approach calls for enhancing architectures with the resources
needed to make the execution of the most frequent and the most time-consuming oper-
ations most efficient. The seed for the RISC approach started as early as the mid-
1970s. Its real-life manifestation appeared in the Berkeley RISC-I and the Stanford
MIPS machines, which were introduced in the mid-1980s. Today, RISC-based
machines are reality and they are characterized by a number of common features
such as simple and reduced instruction set, fixed instruction format, one instruction
per machine cycle, pipeline instruction fetch

/

execute units, ample number of general
purpose registers (or alternatively optimized compiler code generation), Load

/

Store
memory operations, and hardwired control unit design. Our coverage in this chapter
starts with a discussion on the evolution of RISC architectures. We then provide a
brief discussion on some of the performance studies that led to the adoption of the
RISC paradigm. Overlapped Register Windows, an essential concept in the RISC
development, is then discussed. Toward the end of the chapter we provide details
on a number of RISC-based architectures, such as the Berkeley RISC, the Stanford
MIPS, the Compaq Alpha, and the SUN UltraSparc.

/

10.1. RISC / CISC EVOLUTION CYCLE

The term RISCs stands for Reduced Instruction Set Computers. It was originally
introduced as a notion to mean architectures that can execute as fast as one