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Figure 9.21 A carry-save based multiplication of two 8-bit operands M and Q
each performing an operation from EC, EA, AD, and NZ. Figure 9.19 shows a sche-
matic for a pipeline FP adder. It is possible to have multiple sets of FP operands pro-
ceeding inside the adder at the same time, thus reducing the overall time needed for
FP addition. Synchronizing latches are needed, as before, in order to synchronize the
operands at the input of a given stage in the FP adder.
9.5.3. Pipelined Multiplication Using Carry-Save Addition
As indicated before, one of the main problems with addition is the fact that the carry
has to ripple through from one stage to the next. Carry rippling through stages can be
eliminated using a method called carry-save addition. Consider the case of adding
44, 28, 32, and 79. A possible way to add these without having the carry ripple
through is illustrated in Figure 9.20. The idea is to delay the addition of the carry
resulting in the intermediate stages until the last step in the addition. Only at the
last stage is a carry-ripple stage employed.
A
B
Latches
Partial Product Generator Circuit
Full Adder
Full Adder
Latches
Full Adder
Full Adder
Latches
Full Adder
Latches
CLA
Figure 9.22 Carry-save addition-based multiplication scheme
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