Pipelining Design Techniques - Fundamentals of Computer Organization and Architecture - page 190

have also to wait (at the output of the IF unit) until such time that instruction I i þ 1
proceeds to the ID. The net result is that pipeline stall takes place due to the data
dependency that exists between instruction I i and instruction I i þ 1 .
The data dependency presented in the above example resulted because register R 3
is the destination for both instructions I i and I i þ 1 . This is called a write-after-write
data dependency. Taking into consideration that any register can be written into
(or read from), then a total of four different possibilities exist, including the
write-after-write case. The other three cases are read-after-write, write-after-read,
and read-after-read. Among the four cases, the read-after-read case should not
lead to pipeline stall. This is because a register read operation does not change
the content of the register. Among the remaining three cases, the write-after-write
(see the above example) and the read-after-write lead to pipeline stall. The following
piece of code illustrates the read-after-write case:

ADD

R 1 , R 2 , R 3 ; R 3 R 1 þ R 2

SUB R 3 ,1,R 4 ; R 4 R 3 2 1

†

In this case, the first instruction modifies the content of register R 3 (through a
write operation) while the second instruction uses the modified contents of R 3
(through a read operation) to load a value into register R 4 . While these two
instructions are proceeding within a pipeline, care should be taken so that the
value of register R 3 read in the second instruction is the updated value resulting
from execution of the previous instruction. Figure 9.6 shows the Gantt's chart for
this case assuming that the first instruction is called I i and the second instruction
is called I i þ 1 .
It is clear that the operand of the second instruction cannot be fetched during time
unit k þ

5. This is because the modi-
fied value of the content of register R 3 will not be available until time slot k þ

3 and that it has to be delayed until time unit k þ

5.

I i +1

IS

I i

IE

I i I i +1

OF

I i I i +1

I i I i +1

ID

I i I i +1

IF

kk + 1 k + 2 k + 3 k + 4 k + 5 k + 6 Time

Figure 9.6 The read-after-write data dependency