Information Technology Reference
In-Depth Information
& CHAPTER 9
Pipelining Design Techniques
There exist two basic techniques to increase the instruction execution rate of a pro-
cessor. These are to increase the clock rate, thus decreasing the instruction execution
time, or alternatively to increase the number of instructions that can be executed
simultaneously. Pipelining and instruction-level parallelism are examples of the
latter technique. Pipelining owes its origin to car assembly lines. The idea is to
have more than one instruction being processed by the processor at the same
time. Similar to the assembly line, the success of a pipeline depends upon dividing
the execution of an instruction among a number of subunits (stages), each perform-
ing part of the required operations. A possible division is to consider instruction
fetch (F), instruction decode (D), operand fetch (F), instruction execution (E),
and store of results (S) as the subtasks needed for the execution of an instruction.
In this case, it is possible to have up to five instructions in the pipeline at the
same time, thus reducing instruction execution latency. In this Chapter, we discuss
the basic concepts involved in designing instruction pipelines. Performance
measures of a pipeline are introduced. The main issues contributing to instruction
pipeline hazards are discussed and some possible solutions are introduced. In
addition, we introduce the concept of arithmetic pipelining together with the prob-
lems involved in designing such a pipeline. Our coverage concludes with a review of
a recent pipeline processor.
9.1. GENERAL CONCEPTS
Pipelining refers to the technique in which a given task is divided into a number of
subtasks that need to be performed in sequence. Each subtask is performed by a
given functional unit. The units are connected in a serial fashion and all of them
operate simultaneously. The use of pipelining improves the performance compared
to the traditional sequential execution of tasks. Figure 9.1 shows an illustration of the
basic difference between executing four subtasks of a given instruction (in this case
fetching F, decoding D, execution E, and writing the results W) using pipelining and
sequential processing.
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