Input–Output Design and Organization - Fundamentals of Computer Organization and Architecture - page 178

bus using a technique called handshaking. The operations of synchronous and asyn-
chronous buses are explained below.
To understand the difference between synchronous and asynchronous, let us con-
sider the case when a master such as a CPU or DMA is the source of data to be trans-
ferred to a slave such as an I

O device. The following is a sequence of events

/

involving the master and slave:

1. Master: send request to use the bus
2. Master: request is granted and bus is allocated to master
3. Master: place address

data on bus

/

4. Slave: slave is selected
5. Master: signal data transfer
6. Slave: take data
7. Master: free the bus

8.5.1. Synchronous Buses

In synchronous buses, the steps of data transfer take place at fixed clock cycles.
Everything is synchronized to bus clock and clock signals are made available to
both master and slave. The bus clock is a square wave signal. A cycle starts at
one rising edge of the clock and ends at the next rising edge, which is the beginning
of the next cycle. A transfer may take multiple bus cycles depending on the speed
parameters of the bus and the two ends of the transfer.
One scenario would be that on the first clock cycle, the master puts an address on
the address bus, puts data on the data bus, and asserts the appropriate control lines.
Slave recognizes its address on the address bus on the first cycle and reads the new
value from the bus in the second cycle.
Synchronous buses are simple and easily implemented. However, when connect-
ing devices with varying speeds to a synchronous bus, the slowest device will deter-
mine the speed of the bus. Also, the synchronous bus length could be limited to
avoid clock-skewing problems.

8.5.2. Asynchronous Buses

There are no fixed clock cycles in asynchronous buses. Handshaking is used instead.
Figure 8.11 shows the handshaking protocol. The master asserts the data-ready line

Data-Bus Data Data Data

3 1 3

Data-ready 1

4 2 4

Data-accept 2

Figure 8.11 Asynchronous bus timing using handshaking protocol