Input–Output Design and Organization - Fundamentals of Computer Organization and Architecture - page 173

TABLE 8.2 Interrupt Vector Table

Exception type Mode Address

Reset Supervisor 0 00000000

Undefined instructions Undefined 0 00000004

Software interrupts (SWI) Supervisor 0 00000008

Prefetch abort Abort 0 0000000C

Data abort Abort 0 00000010

IRQ (Normal interrupt) IRQ 0 00000018

FIQ (Fast interrupt) FIQ 0 0000001C

86, the addresses of the interrupt handlers are stored in a vector
table, which is shown in Table 8.2. For example, when an IRQ is detected by the core,
it accesses address 0

Similar to the 80

18 of the vector table and executes the instruction loaded in that
address. Normally, the instruction found at 0 18 of the vector table is of the form:

LDR PC, IRQ_Handler (load the address of the IRQ interrupt handler in the PC).
When an FIQ is detected by the core, it accesses address 0

1C of the vector table
and executes the instruction loaded in that address. Normally, the instruction found
at 0 1C of the vector table is of the form: LDR PC, FIQ_Handler.

When an interrupt occurs, the following happens inside the core:

1. The CPSR (current program state register) is copied to the SPSR (saved pro-
gram status register) of the mode being entered.
2. The CPSR bits are set as appropriate to the mode being entered, the core is set
to ARM state, and the relevant interrupt disable flags are set.
3. The appropriate set of banked registers are banked in.
4. The return address is stored in the link register (of the relevant mode).
5. The PC is set to the relevant vector address.

For example, when an IRQ interrupt is detected, the ARM core enables SPSR_irq as
the CPSR, enters the IRQ mode by setting the mode bits in the CSPR to 10010, dis-
ables Normal interrupts by setting the I bit in the CPSR, saves the address of the next
instruction R14_irq, and loads 0

18, an instruction
will load the address of the interrupt handler into the PC. Similarly, when an FIQ
interrupt is detected, the ARM core enables SPSR_fiq as the CPSR, enters the
FIQ mode by setting the mode bits in the CSPR to 10001, disables Normal and
Fast interrupts by setting the F and I bits in the CPSR, saves the address of the
next instruction R14_fiq, and loads 0

18 into the PC. At address 0

1C into the PC. At address 0 1C, an instruc-

tion will load the address of the interrupt handler into the PC.

MC9328MX1 / MXL AITC MXL AITC contains twenty-six

32-bit registers, which are described in Table 8.3. Using these registers, the AITC
allows the selection of whether a pending interrupt source will create a Normal
interrupt (IRQ) or a Fast interrupt (FIQ) to the core. This is accomplished via the

The MC9328MX1 /