Memory System Design II - Fundamentals of Computer Organization and Architecture - page 159

Figure 7.21 Computer system with cache and paged virtual memory

this maximum value. Assume that each page in the virtual memory consists of
64 words, and that 2K words of the main memory are allocated for storing data
during this computation. Suppose that it takes 100 ms to load a page from the
disk into the main memory when a page fault occurs.
(a) Write a simple piece of code (in a notational form) that can perform the
above job.
(b) How many page faults would occur if the elements of the array are stored
in column order in the virtual memory?
(c) How many page faults would occur if the elements of the array are stored
in row order in the virtual memory?
(d) Estimate the total time needed to perform this normalization for both
arrangements (b) and (c).
3. Design a 64M

1- bit static RAM
chips. Assume that each individual chip has a chip select (CS) line and a
read

8-bit memory using a number of 16M

write (R = W) line. Compute the number of chips required and show a

complete connection diagram of the designed memory.
4. Consider the following stream of page requests: 1,2,3,4,5,1,2,3,4,5,1,2,3,4,5.
Assume that the main memory consists of FOUR page frames. Show a trace
of the status of the page frames in the MM and estimate the hit ratio assuming
each of the following page replacement algorithms.
(a) FIFO
(b) LRU
(c) FINUFO
5. Consider the case of a two-dimensional 20 20 array A. The array is stored
column-major. For FIVE main memory page frames, compute how many

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