Memory System Design II - Fundamentals of Computer Organization and Architecture - page 158

TABLE 7.4 Characteristics of Different ROM Implementations

Typical
applications ROM type Cost Programmability

Mask-programmed ROM Truly inexpensive Once at manufacture Microcode

PROM Inexpensive Once on site Prototyping

EPROM Moderate Many times Prototyping

FEPROM Expensive Many times VCR & TVs

EEPROM Truly expensive Many times VCR & TVs

7.4. SUMMARY

The discussion in this chapter has been a continuation of that conducted in Chapter 6.
In particular, this chapter has been dedicated to cover the design aspects that relate to
the internal and external organization of the main memory. The design of a static
RAM cell was introduced with emphasis on the read and write operations. Our dis-
cussion on virtual memory started with the issues related to address translation.
Three address translation techniques were discussed and compared. These are the
direct, associative, and the set-associative techniques. The use of a TLB to improve
the average access time was explained. Three replacement techniques were intro-
duced. These are the FIFO, LRU, and clock replacement. Segmented paged systems
were also introduced. Our discussion on virtual memory ended with an explanation
of the virtual memory aspects of the Pentium IV processor. Toward the end of the
chapter, we have touched on a number of implementations for ROMs.

EXERCISES

1. Consider the case of a computer system employing both a cache and a paged
virtual memory as shown below (Fig. 7.21). One can analyze this system
through identifying FIVE combinations of accesses. What are these combi-
nations? Determine the probability and the access time in each case assuming
the following information. Compute also the overall average access time.

TLB address translation and search 25 ns

Cache search time to determine whether address in cache 25 ns

Cache access time 25 ns

Main memory access time 250 ns

Hard disk access time 100 ms

TLB hit ratio 0.9

Cache hit ratio 0.95

Main memory hit ratio 0.8

2. A 64 64 array of words (elements) is to be “normalized” as follows. For each

row, the largest element is found and all elements of the row are divided by