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indicate where to place the incoming page and a used bit to indicate the usage of a
given page. The technique can be explained using the following three steps.
1. If the used bit
1, then reset bit, increment pointer and repeat.
¼
2. If the used bit
0, then replace corresponding page and increment pointer.
3. The used bit is SET if the page is referenced after the initial loading.
¼
Example
Consider the following page requests (Fig. 7.16) in a THREE-page
frames MM system using the FINUFO technique: 2,3,2,4,6,2,5,6,1,4,6. Estimate
the hit ratio. The estimated Hit Ratio
4
11.
¼
/
7.2.6. Virtual Memory Systems with Cache Memory
A typical computer system will contain a cache, a virtual memory, and a TLB. When
a virtual address is received from the processor, a number of different scenarios can
occur, each dependent on the availability of the requested item in the cache, the main
memory, or the secondary storage. Figure 7.17 shows a general flow diagram for the
different scenarios.
The first level of address translation checks for a match between the received vir-
tual address and the virtual addresses stored in the TLB. If a match occurs (TLB hit)
then the corresponding physical address is obtained. This physical address can then
be used to access the cache. If a match occurs (cache hit) then the element requested
by the processor can be sent from the cache to the processor. If, on the other hand, a
cache miss occurs, then the block containing the targeted element is copied from the
main memory into the cache (as discussed before) and the requested element is sent
to the processor.
The above scenario assumes a TLB hit. If a TLB miss occurs, then the page table
(PT) is searched for the existence of the page containing the targeted element in the
main memory. If a PT hit occurs, then the corresponding physical address is gener-
ated (as discussed before) and a search is conducted for the block containing
the requested element (as discussed above). This will require updating the TLB.
If on the other hand a PT miss takes place (indicating a page fault), then the page
containing the targeted element is copied from the disk into the main memory, a
block is copied into the cache, and the element is sent to the processor. This last
Figure 7.16 FINUFO replacement technique
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