Memory System Design II - Fundamentals of Computer Organization and Architecture - page 143

It is useful to mention at this point that although based on similar principles, a
significant difference exists between cache and virtual memories. A cache miss
can cause a time penalty that is 5 to 10 times as costly as a cache hit. A page
fault, on the other hand can be 1000 times as costly as a page hit. It is therefore
unreasonable to have the processor wait on a page fault while a page is being trans-
ferred to the main memory. This is because thousands of instructions could be exe-
cuted on a modern processor during page transfer.
The address issued by the processor in order to access a given word does not
correspond to the physical memory space. Therefore, such address is called a vir-
tual (logical) address. The memory management unit (MMU) is responsible for the
translation of virtual addresses to their corresponding physical addresses. Three
address translation techniques can be identified. These are direct-mapping, associ-
ative-mapping, and set-associative-mapping. In all these techniques, information
about the main memory locations and the corresponding virtual pages are kept
in a table called the page table. The page table is stored in the main memory.
Other information kept in the page table includes a bit indicating the validity of
a page, modification of a page, and the authority for accessing a page. The valid
bit is set if the corresponding page is actually loaded into the main memory.
Valid bits for all pages are reset when the computer is first powered on. The
other control bit that is kept in the page table is the dirty bit. It is set if the corres-
ponding page has been altered while residing in the main memory. If while residing
in the main memory a given page has not been altered, then its dirty bit will be
reset. This can help in deciding whether to write the contents of a page back
into the disk (at the time of replacement) or just to override its contents with
another page. In the following discussion, we will concentrate on the address trans-
lation techniques keeping in mind the use of the different control bits stored in the
page table.
7.2.1. Direct Mapping
Figure 7.9 illustrates the address translation process according to the direct-mapping
technique. In this case, the virtual address issued by the processor is divided into
two fields: the virtual page number and the offset fields. If the number of bits in
the virtual page number field is N, then the number of entries in the page table
will be 2 N .
The virtual page number field is used to directly address an entry in the page
table. If the corresponding page is valid (as indicated by the valid bit), then the con-
tents of the specified page table entry will correspond to the physical page address.
The latter is then extracted and concatenated with the offset field in order to form the
physical address of the word requested by the processor. If, on the other hand, the
specified entry in the page table does not contain a valid physical page number,
then this represents a page fault. In this case, the MMU will have to bring the
corresponding page from the hard disk, load it into the main memory, and indicate
the validity of the page. The translation process is then carried out as explained
before.