Information Technology Reference
In-Depth Information
Another possible organization of the memory cell array is as a 64
64, that is, to
organize the array in the form of 64 rows, each consisting of 64 cells. In this
case, six address lines (forming what is called the row address) will be needed in
order to select one of the 64 rows. The remaining four address lines (called the
column address) will be used to select the appropriate 4 bits among the available
64 bits constituting a row. Figure 7.4 illustrates this organization.
Another important factor related to the design of the main memory subsystem is
the number of chip pins required in an integrated circuit. Consider, for example, the
design of a memory subsystem whose capacity is 4K bits. Different organization of
the same memory capacity can lead to a different number of chip pins requirement.
Table 7.1 illustrates such an observation. It is clear from the table that increasing the
number of bits per addressable location results in an increase in the number of pins
needed in the integrated circuit.
Another factor pertinent to the design of the main memory subsystem is the
required number of memory chips. It is important to realize that the available per
chip memory capacity can be a limiting factor in designing memory subsystems.
W 0
A 0
W 1
A 1
W 2
A 2
64 × 64 memory cell array
A 5
W 63
B 63
B 62
B 2
B 1
B 0
A A A 8
A 9
16 to 1 multiplexers
D 3
D 2
D 1
D 0
Figure 7.4 Efficient internal organization of a 1K 4 memory chip
 
Search WWH ::




Custom Search