Memory System Design II - Fundamentals of Computer Organization and Architecture - page 135

& CHAPTER 7

Memory System Design II

In Chapter 6 we introduced the concept of memory hierarchy. We have also character-
ized a memory hierarchy in terms of the locality of reference and its impact on the aver-
age access time. We then moved on to cover the different issues related to the first level
of the hierarchy, that is, the cache memory (the reader is advised to carefully review
Chapter 6 before proceeding with this chapter). In this chapter, we continue our cover-
age of the different levels of the memory hierarchy. In particular, we start our discus-
sion with the issues related to the design and analysis of the (main) memory unit. Issues
related to virtual memory design are then discussed. A brief coverage of the different
read-only memory (ROM) implementations is provided at the end of the chapter.

7.1. MAIN MEMORY

As the name implies, the main memory provides the main storage for a computer.
Figure 7.1 shows a typical interface between the main memory and the CPU.
Two CPU registers are used to interface the CPU to the main memory. These are
the memory address register (MAR) and the memory data register (MDR). The
MDR is used to hold the data to be stored and

/ or retrieved in / from the memory

location whose address is held in the MAR.
It is possible to visualize a typical internal main memory structure as consisting
of rows and columns of basic cells. Each cell is capable of storing one bit of infor-
mation. Figure 7.2 provides a conceptual internal organization of a memory chip. In
this figure, cells belonging to a given row can be assumed to form the bits of a given
memory word. Address lines A n 1 A n 2 ... A 1 A 0 are used as inputs to the address
decoder in order to generate the word select lines W 2 n 1 ... W 1 W 0 . A given word
select line is common to all memory cells in the same row. At any given time,
the address decoder activates only one word select line while deactivating the
remaining lines. A word select line is used to enable all cells in a row for read or
write. Data (bit) lines are used to input or output the contents of cells. Each
memory cell is connected to two data lines. A given data line is common to all
cells in a given column.