Memory System Design I - Fundamentals of Computer Organization and Architecture - page 131

discussed and their effect on the average access time was explained. Three cache
mapping techniques, namely direct, associative, and set-associative mappings
were analyzed and their performance measures compared. We have also introduced
three replacement techniques: Random, FIFO, and LRU replacement. The impact of
the three techniques on the cache hit ratio was analyzed. Cache writing policies were
also introduced and analyzed. Our discussion on cache ended with a presentation of
the cache memory organization and characteristics of three real-life examples:
Pentium IV, PowerPC, and PMC-Sierra RM7000, processors. In Chapter 7, we
will discuss the issues related to the design aspects of the internal and external
organization of the main memory. We will also discuss the issues related to virtual
memory.

EXERCISES

1. Determine the memory interleaving factor required to obtain an average
access time of less that 60 ns given that the main memory has an access
time of 100 ns and the cache has an access time of 20 ns. What is the average
access time of the resulting system?
2. What is the average access time of a system having three levels of memory, a
cache memory, a semiconductor main memory, and a magnetic disk second-
ary memory, if the access times of the memories are 20 ns, 100 ns, and 1 ms,
respectively. The cache hit ratio is 90% and the main memory hit ratio is 95%.
3. A computer system has an MM consisting of 16 MB 32-bit words. It also has
an 8 KB cache. Assume that the computer uses a byte-addressable mechan-
ism. Determine the number of bits in each field of the address in each of
the following organizations:
(a) Direct mapping with block size of one word
(b) Direct mapping with a block size of eight words
(c) Associative mapping with a block size of eight words
(d) Set-associative mapping with a set size of four block and a block size of
one word.
4. Consider the execution of the following program segment on an 8

8 array A.

For i: ¼ 0to7do
SUM: ¼ 0
For j: ¼ 0to7do
SUM: ¼ SUM þ A(i,j)
End for
AVE(i): ¼ SUM / 8
End for
Assume that the main memory is divided into eight interleaved memory
blocks and that each cache memory block consists of eight elements.
Assume also that the cache memory access time is 10 ns and that the
memory access time is ten times the cache memory access time. Compute
the average access time per element of the array A.