Memory System Design I - Fundamentals of Computer Organization and Architecture - page 110

(a small high-speed memory that is near the CPU). The end result is that at any given
time some active portion of the main memory is duplicated in the cache. Therefore,
when the processor makes a request for a memory reference, the request is first
sought in the cache. If the request corresponds to an element that is currently resid-
ing in the cache, we call that a cache hit. On the other hand, if the request corre-
sponds to an element that is not currently in the cache, we call that a cache miss.
A cache hit ratio, h c , is defined as the probability of finding the requested element
in the cache. A cache miss ratio (1

h c ) is defined as the probability of not finding
the requested element in the cache.
In the case that the requested element is not found in the cache, then it has to be
brought from a subsequent memory level in the memory hierarchy. Assuming that
the element exists in the next memory level, that is, the main memory, then it has
to be brought and placed in the cache. In expectation that the next requested element
will be residing in the neighboring locality of the current requested element (spatial
locality), then upon a cache miss what is actually brought to the main memory is a
block of elements that contains the requested element. The advantage of transferring
a block from the main memory to the cache will be most visible if it could be poss-
ible to transfer such a block using one main memory access time. Such a possibility
could be achieved by increasing the rate at which information can be transferred
between the main memory and the cache. One possible technique that is used to
increase the bandwidth is memory interleaving. To achieve best results, we can
assume that the block brought from the main memory to the cache, upon a cache
miss, consists of elements that are stored in different memory modules, that is,
whereby consecutive memory addresses are stored in successive memory modules.
Figure 6.2 illustrates the simple case of a main memory consisting of eight memory
modules. It is assumed in this case that the block consists of 8 bytes.
Having introduced the basic idea leading to the use of a cache memory, we would
like to assess the impact of temporal and spatial locality on the performance of
the memory hierarchy. In order to make such an assessment, we will limit our

M 7 M 6 M 5 M 4 M 3 M 2 M 1 M 0

Byte

Main memory

Block

Cache
Figure 6.2 Memory interleaving using eight modules