Processing Unit Design - Fundamentals of Computer Organization and Architecture - page 103

Encoding Source 1 Destination Encoding Source 2

01011 R 11 R 11 01011 R 11

01100 R 12 R 12 01100 R 12

01101 R 13 R 13 01101 R 13

01110 R 14 R 14 01110 R 14

01111 R 15 R 15 01111 R 15

10000 PC PC 10000 None

10001 IR IR

10010 MAR MAR

10011 MDR MDR

10100 NONE NONE

Figure 5.14 is the microinstruction for Add R 1 , R 2 , R 0 using the three-bus data-
path under vertical organization:

Example 5 Using the same encoding of Example 4, let us find vertical microin-

structions used in fetching an instruction.

MAR PC First, we need to select PC as source 1 by using “10000” for source 1

field. Similarly, we select MAR as our destination by using “10010” in the destina-
tion field. We also need to use “0000” for the ALU field, which will be decoded to
“NONE”. As shown in the ALU encoding table (Example 4), “NONE” means that
out-bus1 will be connected to in-bus. The field source 2 will be set to “10000”,
which means none of the registers will be selected. The microinstruction is shown
in Figure 5.15.

Memory Read and Write Memory operations can easily be accommodated by
adding 1 bit for read and another for write. The two microinstructions in
Figure 5.16 perform memory read and write, respectively.

Fetch Fetching an instruction can be done using the three microinstructions of
Figure 5.17.
The first and second microinstructions have been shown above. The third microin-
struction moves the contents of the MDR to IR (IR

MDR). MDR is selected as
source 1 by using “10011” for source 1 field. Similarly, IR is selected as the destina-
tion by using “10001” in the destination field. We also need to use “0000” (“NONE”)

Figure 5.14 Microinstruction for Add R 1 , R 2 , R 0

Figure 5.15 Microinstruction for MAR PC