Processing Unit Design - Fundamentals of Computer Organization and Architecture - page 94

Step Micro-operation

t 0 MAR X

t 1 MDR Mem[MAR]

t 2 A (R 0 )

t 3 B (MDR)

t 4 R 0 (A) þ (B)

Using the two-bus datapath shown in Figure 5.4a, this addition will take four
steps as shown below, where t 0 , t 1 , t 2 , t 3 .

Step Micro-operation

t 0 MAR X

t 1 MDR Mem[MAR]

t 2 A (R 0 ) þ (MDR)

t 3 R 0 (A)

Using the two-bus datapath with in-bus and out-bus shown in Figure 5.4b, this
addition will take four steps as shown below, where t 0 , t 1 , t 2 , t 3 .

Step Micro-operation

t 0 MAR X

t 1 MDR Mem[MAR]

t 2 A (R 0 )

t 3 R 0 (A) þ (MDR)

Using the three-bus datapath shown in Figure 5.5, this addition will take three
steps as shown below, where t 0 , t 1 , t 2 .

Step Micro-operation

t 0 MAR X

t 1 MDR Mem[MAR]

t 2 R 0 R 0 þ (MDR)

5.4.3. Interrupt Handling

After the execution of an instruction, a test is performed to check for pending inter-
rupts. If there is an interrupt request waiting, the following steps take place:

1. The contents of PC are loaded into MDR (to be saved).
2. The MAR is loaded with the address at which the PC contents are to be saved.
3. The PC is loaded with the address of the first instruction of the interrupt hand-
ling routine.