Processing Unit Design - Fundamentals of Computer Organization and Architecture - page 93

Using the one-bus datapath shown in Figure 5.3, this addition will take three steps
as shown in the following table, where t 0 , t 1 , t 2 .

Step Micro-operation

t 0 A (R 1 )

t 1 B (R 2 )

t 2 R 0 (A) þ (B)

Using the two-bus datapath shown in Figure 5.4a, this addition will take two steps
as shown in the following table, where t 0 , t 1 .

Step Micro-operation

t 0 A (R 1 ) þ (R 2 )

t 1 R 0 (A)

Using the two-bus datapath with in-bus and out-bus shown in Figure 5.4b, this
addition will take two steps as shown below, where t 0 , t 1 .

Step Micro-operation

t 0 A (R 1 )

t 1 R 0 (A) þ (R 2 )

Using the three-bus datapath shown in Figure 5.5, this addition will take only one
step as shown in the following table.

Step Micro-operation

t 0 R 0 (R 1 ) þ (R 2 )

Add X, R 0 This instruction adds the contents of memory location X to register R 0
and stores the result in R 0 . This addition can be executed as follows:

1. The memory location X is extracted from IR and loaded into MAR.
2. As a result of memory read operation, the contents of X are loaded into MDR.
3. The contents of MDR are added to the contents of R 0 .

Using the one-bus datapath shown in Figure 5.3, this addition will take five steps
as shown below, where t 0 , t 1 , t 2 , t 3 , t 4 .