Processing Unit Design - Fundamentals of Computer Organization and Architecture - page 92

The basic actions during fetching an instruction, executing an instruction, or hand-
ling an interrupt are defined by a sequence of micro-operations. A group of control
signals must be enabled in a prescribed sequence to trigger the execution of a micro-
operation. In this section, we show the micro-operations that implement instruction
fetch, execution of simple arithmetic instructions, and interrupt handling.

5.4.1. Fetch Instructions

The sequence of events in fetching an instruction can be summarized as follows:

1. The contents of the PC are loaded into the MAR.
2. The value in the PC is incremented. (This operation can be done in parallel
with a memory access.)
3. As a result of a memory read operation, the instruction is loaded into the MDR.
4. The contents of the MDR are loaded into the IR.

Let us consider the one-bus datapath organization shown in Fig. 5.3. We will see
that the fetch operation can be accomplished in three steps as shown in the table
below, where t 0 , t 1 , t 2 . Note that multiple operations separated by “;” imply
that they are accomplished in parallel.

Step Micro-operation

t 0 MAR (PC); A (PC)

t 1 MDR Mem[MAR]; PC (A) þ 4

t 2 IR (MDR)

Using the three-bus datapath shown in Figure 5.5, the following table shows the
steps needed.

Step Micro-operation

t 0 MAR (PC); PC (PC) þ 4

t 1 MDR Mem[MAR]

t 2 IR (MDR)

5.4.2. Execute Simple Arithmetic Operation

Add R 1 ,R 2 ,R 0 This instruction adds the contents of source registers R 1 and R 2 ,and
stores the results in destination register R 0 . This addition can be executed as follows:

1. The registers R 0 , R 1 , R 2 , are extracted from the IR.
2. The contents of R 1 and R 2 are passed to the ALU for addition.
3. The output of the ALU is transferred to R 0 .