Processing Unit Design - Fundamentals of Computer Organization and Architecture - page 89

5.3. DATAPATH

The CPU can be divided into a data section and a control section. The data section,
which is also called the datapath, contains the registers and the ALU. The datapath is
capable of performing certain operations on data items. The control section is basi-
cally the control unit, which issues control signals to the datapath. Internal to the
CPU, data move from one register to another and between ALU and registers.
Internal data movements are performed via local buses, which may carry data,
instructions, and addresses. Externally, data move from registers to memory and
I O devices, often by means of a system bus. Internal data movement among

registers and between the ALU and registers may be carried out using different
organizations including one-bus, two-bus, or three-bus organizations. Dedicated
datapaths may also be used between components that transfer data between them-
selves more frequently. For example, the contents of the PC are transferred to the
MAR to fetch a new instruction at the beginning of each instruction cycle. Hence,
a dedicated datapath from the PC to the MAR could be useful in speeding up this
part of instruction execution.

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5.3.1. One-Bus Organization

Using one bus, the CPU registers and the ALU use a single bus to move outgoing
and incoming data. Since a bus can handle only a single data movement within
one clock cycle, two-operand operations will need two cycles to fetch the operands
for the ALU. Additional registers may also be needed to buffer data for the ALU.
This bus organization is the simplest and least expensive, but it limits the
amount of data transfer that can be done in the same clock cycle, which will slow
down the overall performance. Figure 5.3 shows a one-bus datapath consisting of
a set of general-purpose registers, a memory address register (MAR), a memory
data register (MDR), an instruction register (IR), a program counter (PC), and
an ALU.

Program Counter (PC), and ALU

A B

PC

IR

General
Purpose
Registers

MAR

ALU

MDR

Memory
Bus

Figure 5.3 One-bus datapath