Processing Unit Design - Fundamentals of Computer Organization and Architecture - page 87

5.2.5. 80 3 86 Registers
As discussed in Chapter 3, the Intel basic programming model of the 386, 486, and the
Pentium consists of three register groups. These are the general-purpose registers, the
segment registers, and the instruction pointer (program counter) and the flag register.
Figure 5.2 (which repeats Fig. 3.6) shows the three sets of registers. The first set
consists of general purpose registers A, B, C, D, SI (source index), DI (destination
index), SP (stack pointer), and BP (base pointer). The second set of registers consists
of CS (code segment), SS (stack segment), and four data segment registers DS, ES,
FS, and GS. The third set of registers consists of the instruction pointer (program
counter) and the flags (status) register. Among the status bits, the first five are iden-
tical to those bits introduced as early as in the 8085 8-bit microprocessor. The next
6-11 bits are identical to those introduced in the 8086. The flags in the bits 12-14
were introduced in the 80286 while the 16-17 bits were introduced in the 80386.
The flag in bit 18 was introduced in the 80486.

5.2.6. MIPS Registers

The MIPS CPU contains 32 general-purpose registers that are numbered 0-31.
Register x is designated by $x. Register $zero always contains the hardwired
value 0. Table 5.1 lists the registers and describes their intended use. Registers
$at (1), $k0 (26), and $k1 (27) are reserved for use by the assembler and operating
system. Registers $a0-$a3 (4-7) are used to pass the first four arguments to routines

Figure 5.2 The main register sets in 80 86 (80386 and above extended all 16 bit registers

except segment registers)