A Low Power, Programmable Networking Platform and Development Environment - Advances in Network-Embedded Management and Applications - page 29

4.2 Custom module development

The development of the new applications is also assisted by a number of
available hardware component models that can be used for generic
networking application development. The already available components
define a generic packet processing/forwarding architecture with extensible
filtering and processing properties, and a generic deep packet inspection
architecture. All components come with SystemC and VHDL source code and
IP-XACT description. The extensible, modular architectures are designed to
allow easy integration of application-specific header operations at the ingress
and egress. A method for buffering the packet payload is also provided. Most
of the applications can be covered with the available modules. The
architecture also features a hierarchical power management concept for low
power operation [14].
However, if a custom module is needed for a hardware-level operation
which is not yet available, new modules can be created and added to the
model database by adding the source files to the SystemC and VHDL
directories and creating the IP-XACT XML descriptor. The key issues are the
interfaces of the new component, and the timing requirements. For the most
common operations like input/output processing and flow handling well
defined interfaces are provided with low timing requirements. However, for
line-speed processing all modules must handle back-to-back packet arrivals at
interface speeds. For even easier development generic filter prototypes are
provided with full source code. First, the SystemC model should be created,
for composability and predictability checking. Based on the SystemC model
the HDL model can be created too, and added to the HDL model database.

4.3 Hardware accelerator development

The protocol processing task usually starts with basic input/output operations
like packet reception and queuing. These operations require hardware
processing, for fastest execution. After several stages of header processing, it
may not be suitable for hardware processing because of increased complexity;
software processing is more flexible and desirable. The conventional
networking protocols had simple structure, binary headers and fixed fields.
As we climb the levels of the OSI model, the protocols become more and
more complicated, with variable header lengths and fields. One of the most
difficult protocols to decode are the textual protocols like HTTP and SIP,
where very few things are fixed, fields can be mixed, string identifiers are
used and all fields have variable length. Such protocols require software
processing, involving parsing. There are several methods to enhance the
processing in hardware with accelerator interfaces. Different protocols require