Information Technology Reference
In-Depth Information
consumption depends on the clock frequency as well. The C-board is
configured to operate on the lowest frequency on which it is able to process
all of the traversing packets on 10 Gbps interface.
Furthermore, lower power consumption can be reached by close power
control of the programmable devices in a dynamic manner, while they
operate. There are three areas in the SCALOPES C-board where such
Dynamic Power Control (DPC) can be administered: the interfaces, the FPGA
and the memory. DPC is managed by a central resource manager (governor)
application, residing in the compact PC.
Naturally, if an Ethernet interface is not configured to be working in a
given configuration (runtime), its controller is shut down, not consuming any
power. Moreover, the Ethernet interfaces connect to the FPGA chips in a
distributed manner, which means if the related interfaces are not needed, the
corresponding FPGA chip can be assigned to stand-by mode, hence
significantly decreasing the system's energy consumption. This power
reduction scheme can be initiated runtime, in connection with the network
configuration changes.
Internally to the FPGAs, power islands are defined for segregated
functions: interface handling, packet filtering modules, management modules
and low-speed/high-speed implementations of packet processing algorithms
(depending on timing criteria, the low-speed implementation might be used
for power considerations). Based on the running application and the traffic
volumes the central power governor can decide to shutting down or waking up
these islands.
DDR RAM memory is connected to the FPGAs, and its power-
management can also be controlled from there, runtime: it can be set to stand-
by or power down mode if a given application does not need to use the
external memory.
In order to measure power consumption, sensors are placed at key areas of
the hardware. These sensors send signals about the measured signals to the
management interface, where the data can be collected, analyzed and used for
system tuning.
4
The Development Environment
Developing or even modifying complex networking systems that consist of
hardware and software processing modules require either incredible
experience or extreme braveness - sometimes both. In order to develop
applications to the SCALOPES C-board, efficient hardware and software co-
design methodology must be administered.
Our approach follows a two-step process in the high-level, and based on
elemental building blocks of a modular architecture. The first step in the
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