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available in the field, nevertheless, upto this date we have not found another
platform that
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is both programmable in hardware and software,
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can manipulate the traffic by utilizing PCIe-connected controllers,
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has capabilities to directly forward 10Gbps Ethernet traffic to/from 1Gbps
Ethernet or SONET,
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is designed for measurable low power consumption, and
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has lowered risks for extra developments since composability,
predictability and dependability [2] issues are tackled.
The SCALOPES C-board was designed and developed with the ultimate
intention of putting the above requirements into practice.
3.2
Internal Structure
The practical capabilities of any networking equipment are limited by its
internal elements, their programmability, and its interfaces' types, modes, and
speed. During the development of the SCALOPES C-board, the requirements
were set high: it is a highly scalable device with a well-defined programming
toolchain, capable of manipulating traffic arriving from SONET, ATM,
Gigabit and 10 Gigabit Ethernet, routing/switching the traffic between these
interfaces and further controlling or processing it through PCIe x4 extension
modules. The simplified architecture of the board is depicted by
Fig. 1
.
The main components of the device are the following:
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XFPs (10 Gigabit Small Form Factor Pluggable Modules) connecting to
XAUIs (10 Gigabit Attachment Unit Interface) for 10 Gbps traffic
reception,
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SFPs (Small Form/factor Pluggables) to handle various Gigabit Ethernet
ports, for output to devices,
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four FPGAs (Field-Programmable Gate Arrays) connected in a matrix,
used for packet capture and manipulation, including interface handling,
traffic flow handling firmware blocks, basic statistical modules,
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memory for packet buffering and flow tables,
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extra processor for on-board processing and management software,
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redundant power supply.
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