A Low Power, Programmable Networking Platform and Development Environment - Advances in Network-Embedded Management and Applications - page 22

study on real-application behavior under a wide range of specific network
conditions, such as file transfer, Internet telephony (VoIP) and video
streaming. Other approaches include hardware accelerated routing, e.g. the
work of D. Antos et al. [7] on the design of lookup machine of a hardware
router for IPv6 and IPv4 packet routing with operations are performed by
FPGA. In this framework, part of the packet switching functionality is moved
into the hardware accelerator, step by step. This allows keeping the complete
functionality all the time, only increasing the overall speed of the system
during the whole development process. D. Teuchert et al. [8] also dealt with
FPGA based IPv6 lookup using a pipelined, tree-bitmap algorithm based
method.
The NetFPGA project also provides a development environment for the
programmable hardware platform. Their approach [10] is to provide reference
architectures (interface card, switch, router, etc.) as starting points for new
development. To avoid the necessity of hardware level programming and
provide a high level interface, a framework is presented in [11] to incorporate
hardware G modules into NetFPGA based system designs.
Although there are several similar approaches [9], none of them fulfills the
requirements of the C-Board. The existing hardware is not fast or not scalable
enough, while also the development environment lacks the flexibility and the
required simplicity.

3 The SCALOPES C-board

The ARTEMIS SCALOPES project aims at developing and utilizing novel
methods in low power, high performance embedded platforms. Our
SCALOPES C-board is the prototype platform for the communication
infrastructure-related applications inside the project. The main purpose of the
C-board is to provide a basis for high-speed data processing and manipulation.
It could either host or serve monitoring, switching, routing, filtering and other
applications that require real-time processing of 10 Gigabit Ethernet traffic. In
the following sections the motivations, requirements and the state of the art is
surveyed, followed by the brief description of the architecture.

3.1 Motivation and Requirements

Real time analysis and manipulation of 10 Gigabit Ethernet traffic requires
scalable, high performance equipment. Clear and easy-to-use management
and programming interfaces further ease the task of the user of such
equipment. There are some programmable networking platforms already