Information Technology Reference
In-Depth Information
1
Introduction
Networking at ever growingly high-rate connections constantly generates
challenges for researchers and engineers developing algorithms and
equipment to handle the demands of networking services. The increasing rate
is not the only concern, but it brings some general, seemingly far-away
problems into the limelight.
When data arrives to a system at 10 Gigabit per second rate, the time is
very limited for analyzing or handling it. Moreover, there is no point for its
single storage for further analysis (except for some targeted analysis). If the
system cannot process continuously arriving data, it will not be able to
process it later, when further data still arrives continuously. To optimize data
processing in many levels, tasks should be distributed and made parallel. The
processing level here does not only mean OSI levels, but levels of processing
complexity determined by the given task. Examples for such tasks are flow
assembly based on TCP- and IP-headers, routing and switching between
interfaces, application classification by using DPI (Deep Packet Inspection),
etc. Our system utilizes multiple processors with various capabilities for
processing network traffic in various levels. The capabilities on the main
board are distributed through FPGAs (used for time-stamping and initial
packet header processing) and a general processor (used for management
functions, and basic traffic analysis, statistics creation). Processors on the
COM express PC and the PCIe-connected modules can be utilized for
complex processing, including routing, switching and basic DPI. Furthermore,
the system is prepared for very complex DPI (application analysis through
fingerprints, deep flow analysis, etc.), by means of streaming digested packet
and flow-data to external processors through its 1GbE interfaces.
Low power design is a current and very important requirement in all fields,
including IT systems. The high demand for networking services is covered by
ever increasing number of servers and networking equipment, which, if left
uncontrolled, waste electrical power and simply turns it into heat. On the other
hand, handling or analyzing high speed traffic requires high performance,
which is by definition a term competing with low power consumption. The
challenge of high-performance, yet low-power systems is to find out which
costs less power: should we shut down resources that are not in use and
urgently wake them up when required or should we leave the resource
running. Measuring power consumption and optimization for low power with
high performance was a very key requirement during the definition and design
of our system.
We have also created a development environment together with the
platform. The aim of this is to accelerate the development process of network
applications on FPGAs in general. The environment provides a GUI and a set
of hardware modules which builds up a variety of network devices. Key use-
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