Simulation Still Rules: Modern Computer Systems Architecture Visualized and Laid Bare - 2nd International Workshop on Evidence-Based Technology Enhanced Learning - page 96

Figure 9 (left) is a snapshot of resource utilization display with two CPUs shar-
ing the processes and can be used to demonstrate and explore CPU load balancing.
A consequence of managing multiple processes and finite resources is the possi-
bility of deadlocking. The OS simulator incorporates a deadlock simulator that fa-
cilitates the studying of deadlock prevention, detection and resolution techniques.
Figure 9 (right) is a graphical representation of deadlocked processes P1 to P4.
3.3 'TeachingCompiler'Visualizations
The teaching compiler compiles high-level language statements into assembly in-
structions and the equivalent byte code while at the same time displaying different
stages of compilation process as shown in Figure 10. It is also possible to animate
the tracing of source lines corresponding to the CPU instructions as they are run.
The source editor is at top left; below that is the display of different stages of
the compilation process. The top right image shows the CPU instructions in as-
sembly language format and below that is the byte code equivalent. The students
can highlight a source statement whereupon the corresponding code is highlighted
and vice versa. Selected compilation progress displays are associated with corres-
ponding source statements facilitating understanding as can be seen in Figure 10.
Fig. 10 Example source, corresponding compiler progress display and code generated